Electronic dispersion precompensation of direct-detected NRZ using analog filtering

We demonstrate (in real-time) electrical dispersion compensation in direct detection links using analog transmit side filtering techniques. By this means, we extend the fiber reach using a low complexity solution while avoiding digital preprocessing and digital-to-analog converters (DACs) which are commonly used nowadays. Modulation is done using an IQ MachZehnder modulator (MZM) which allows straightforward compensation of the complex impulse response caused by chromatic dispersion in the fiber. A SiGe BiCMOS 5-tap analog complex finite impulse response (FIR) filter chip and/or a delay between both driving signals of the MZMs is proposed for the filter implementation. Several link experiments are conducted in C-band where transmission up to 60 km of standard single-mode fiber (SSMF) of direct detected 28Gb/s NRZ/OOK is demonstrated. The presented technique can be used in applications where low power consumption is critical

DSP-free and real-time NRZ transmission of 50Gb/s over 15km SSMF and 64Gb/s back-to-back with a 1.3um VCSEL

We demonstrate and analyze 50 Gb/s non-return-to-zero (NRZ) transmission over 15 km of standard single-mode fiber (SSMF), 60-Gb/s NRZ transmission over 5 km of SSMF and up to 64-Gb/s NRZ back-to-back using a directly modulated short-cavity long-wavelength single-mode vertical-cavity surface-emitting laser (VCSEL) emitting at 1326 nm. Owing to an analog 6-tap transmit feedforward equalizer, the link can operate without digital signal processing. In all three cases, real-time bit error ratio measurements below the 7% overhead hard-decision forward error correction threshold are demonstrated when transmitting a pseudorandom bit sequence with a period of 2(7) - 1 bits. In addition, we analyze the interplay between the residual fiber chromatic dispersion at the operating wavelength of the VCSEL and the chirp due to direct modulation. These results demonstrate how O-band, short-cavity long-wavelength single-mode VCSELs can be used in intradata center networks, as well as in interdata center networks at reaches below 15 km

A 4-to-1 240 Gb/s PAM-4 MUX with a 7-tap mixed-signal FFE in 55nm BiCMOS

Next generation high-speed wireline and optical communications will target single lane data rates over 200Gb/s. For this, the generation and transmission of >100 Gbaud PAM-4 is a key step. Recent transmitters in advanced CMOS and FinFET nodes [1,2] provide extensive transmit-side FFE capabilities at respectively 64 and 56Gbaud. Speed limitations in these technologies will make the transition to >100 Gbaud a challenge. Alternatively, InP-based multiplexers like [3] manage to reach >100 Gbaud easily. They also offer the possibility to create high-swing output drivers, necessary to efficiently drive optical modulators. However, InP solutions lack the ability to introduce more complex equalization of the signal. BiCMOS based transmitters like in [4], enable the integration of more complex circuits with respect to InP technologies, are capable to deliver high signal swings required for optical drivers and promise increased bandwidth compared to CMOS/FinFET. This paper presents a 120Gbaud PAM-4 TX incorporating a 7-tap FFE in a 55nm BiCMOS technology. The advantage of the presented FFE architecture is the efficient use of both digital and analog delay structures to obtain >100 Gbaud operation with a large amount of filter taps in a compact configuration

Real-time 28 Gb/s NRZ over 80 km SSMF in C-band using analog electronic precompensation

We demonstrate real-time C-band transmission of direct detected 28Gb/s NRZ/OOK over 80km SSMF using a Dual-Drive MZM and custom-designed SiGe BiCMOS 5-tap analog FIR filters to compensate chromatic dispersion without digital signal processing

Electro-optic frequency response shaping in high speed Mach-Zehnder modulators

We demonstrate a simple technique to shape the electro-optic frequency response of high-speed TW-MZMs. C-band transmission of 56Gb/s NRZ over 3km SSMF shows 5dB power-penalty improvement at KP4-FEC between a standard and shaped MZM design

Electro-optic frequency response shaping using embedded FIR filters in slow-wave modulators

A novel method is presented to embed finite-impulse-response filters in slow-wave Mach-Zehnder modulators. This allows to adjust the electro-optic frequency response to the designer's needs. The filter is embedded by adding optical delay lines and optical crossings between phase shifter segments. The position of the delay lines and crossing in the modulator and the delay line length determine the final response. In this work, we provide a full analysis and modeling approach of the proposed technique and apply it to a silicon photonic modulator. However, the technique is generally applicable to slow-wave modulators and thus not limited to a silicon photonics platform. The modeling is verified using measurements on the manufactured devices. A shaped modulator is used in C-band transmission experiments with 56 Gb/s NRZ data over 3 km fiber to counteract chromatic dispersion and show the advantage over a standard modulator

Analog I/Q FIR filter in 55-nm SiGe BiCMOS for 16-QAM optical communications at 112 Gb/s

We propose a novel implementation of a complex analog equalization filter for the compensation of frequency-dependent variations in coherent optical links. The analog compensation filter can be used in coherent-lite optical communication links where digital signal processing (DSP) is removed to limit the complexity and power consumption. In these links, the filter can compensate for electrical bandwidth limitations and distortion introduced by chromatic dispersion in the fiber. The complex filter is implemented by combining four distributed analog finite-impulse response (FIR) filters to obtain the necessary response. The filter delays are implemented using active delay cell structures to create a compact solution. The analog filter is implemented in a 55-nm BiCMOS technology and consumes 185-mW core power for five complex filter taps. Performance is evaluated using the S-parameter measurements, noise and linearity measurements, and real-time system experiments using 112-Gb/s 16-QAM-modulated signals

A 21-GS/s single-bit second-order delta-sigma modulator for FPGAs

A new high-speed delta-sigma modulator (DSM) topology is proposed by cascading a bit reduction process with a multi-stage noise shaping MASH-1-1 DSM. This process converts the two-bit output sequence of the MASH-1-1 DSM to a single-bit sequence, merely compromising the DSM noise-shaping performance. Furthermore, the high clock frequency requirements are significantly relaxed by using parallel processing. This DSM topology facilitates the designs of wideband software defined radio transmitters and delta-sigma radio-over-fiber transmitters. Experimental results of the FPGA implementation show that the proposed low-pass DSM can operate at 21 GS/s, providing 520-MHz baseband bandwidth with 42.76-dB signal-to-noise-and-distortion ratio (SNDR) or 1.1-GHz bandwidth with 32.04-dB SNDR (based on continuous wave measurements). An all-digital transmitter based on this topology can generate 218.75MBd 256 QAM over 200-m OM4 multimode fiber in real time, with 7-GS/s sampling rate and an error vector magnitude below 1.89%

Adaptive transmit-side equalization for serial electrical interconnects at 100 Gb/s using duobinary

The ever-increasing demand for more efficient data communication calls for new, advanced techniques for high speed serial communication. Although newly developed systems are setting records, off-line determination of the optimal equalizer settings is often needed. Well-known adaptive algorithms are mainly applied for receive-side equalization. However, transmit-side equalization is desirable for its reduced linearity requirements. In this paper, an adaptive sign-sign least mean square equalizer algorithm is developed applicable for an analog transmit-side feed-forward equalizer (FFE) capable of transforming non-return-to-zero modulation to duobinary (DB) modulation at the output of the channel. In addition to the derivation of the update strategy, extra algorithms are developed to cope with the difficult transmit-receive synchronization. Using an analog six tap bit-spaced equalizer, the algorithm is capable of optimizing DB communication of 100Gb/s over 1.5-m Twin-Ax cable. Both simulations and experimental results are presented to prove the capabilities of the algorithm demonstrating automated determination of FFE parameters, such that error-free communication is obtained (BER<10(-13) using PRBS9)